Intern to develop RTL for mix-signal converters and ALU. Responsibilities include functional simulation, verification, and automation using IPXACT MESA flow. Requires Master's in Electrical Engineering and HDL experience.
Intern in Digital IC Design to simulate and evaluate microcontrollers. Responsibilities include developing RTL in SystemVerilog/Verilog, functional simulation, and supporting FPGA prototyping for low-power SoCs.