349 English-speaking jobs in Canton of Vaud

The Invigilator maintains assessment integrity and security at Aiglon College. Key duties include conducting exams per regulations, preventing malpractice, and adhering to safeguarding policies. Candidates must be reliable and detail-oriented.

Strategic analytics and finance partner to EU & WWI Customer Experience & Services leadership. Integrates financial, operational, and customer data to generate insights, evaluate scenarios, and improve Services performance and profitability.

Junior Engineers needed to support data ingestion and customer data workflows. Responsibilities include building scripts, troubleshooting APIs, and ensuring accurate data transfer. Requires skills in Python, SQL, data workflows, and basic programming.

Technical Customer Support Specialist to provide technical advice and solve issues for customers worldwide. This role involves troubleshooting hardware/software, internal hardware referencing, and technical writing. Requires 3-5 years in a technical support role.

Experienced School Counsellor needed for short-term cover (80%). Provide confidential support to students with emotional, social, or adjustment difficulties. Requires Master's degree and professional counselling training.

Associate-Director in FX & DA Trading, responsible for leading the eFX Spot team. Duties include managing operations, PnL, risk, and team development. Requires sell-side electronic FX trading experience.

Postdoc position in ML-Based Co-Design at EPFL. Requires a doctorate in ML, deep knowledge of Control Theory, and a strong publication record in top ML venues. Focus is on co-design for aerodynamic shape and control.

Develop modern Android applications for Payments, Cards, or Cryptocurrencies using Kotlin, Coroutines, Flows, and Jetpack Compose. Build clean, scalable solutions following Clean Architecture principles.

Lead the product and design team for Neho and Strike platforms. Own the product vision, strategy, and roadmap, driving decisions on what to build to shape property buying, selling, and financing in Switzerland.

Support the School Shop and school operations through a 12-month fixed-term contract. Duties include stock takes, Essentials Fair support, and providing flexible assistance for various school needs.

Junior Characterization Engineer to characterize high-speed SerDes IP products. Responsibilities include documenting test results, writing Python automation scripts, and debugging evaluation boards and silicon. Requires 0-3 years of experience.

Own silicon characterization strategy for AI hardware, leading validation plans and execution across product programs. Requires 10+ years in semiconductor IC bring-up, high-speed measurement, and ATE interface development.

Modeling Engineer role requires 7+ years in analog IC design and modeling. Responsibilities include designing circuit models from mathematical description to performance verification, using tools like VerilogA, SystemVerilog, Python, or Matlab.

Digital Design Engineer role focusing on high-speed digital circuits for AI infrastructure. Responsibilities include RTL design, logic synthesis, and verification of complex data-link transceivers and memory interfaces. Requires 5-10 years in digital design.

DFT Engineer role focusing on MBIST/scan insertion, ATPG pattern generation, and coverage analysis. Responsibilities include pattern simulations, timing constraint definition, and debugging silicon issues. Requires 5+ years of DFT experience and knowledge of System Verilog.

Characterization Engineer to lead end-to-end characterization of high-speed SerDes operating at symbol rates above 20 Gbaud. Responsibilities include performing jitter, eye-diagram, BER, and margin measurements, characterizing transmitter and receiver electrical parameters, and collaborating with design teams. Requires proven experience characterizing high-speed SerDes designs, knowledge of TX and RX characteristics, and proficiency with high-speed test equipment. Must have experience with Python for test automation and data analysis.

Lead Analog Layout Engineer needed for custom layout and verification of high-speed analog circuits and IP for multi-Gigabit chip-to-chip communication links in advanced nodes. Requires experience with SerDes, HF/RF circuits, and EDA tools.

Advanced R&D SerDes Architecture and Modeling Engineer to implement and maintain system-level modeling software in MATLAB, Python, and C++. Supports design and verification with analog and digital teams.

Physical Design Engineer to translate high-speed IP digital designs into GDSII layouts for FinFET nodes. Own block-to-chip implementation, meeting PPA targets through synthesis, placement, CTS, and routing. Requires 5+ years in high-speed physical design.

Develop, model, design, and verify custom analog circuits in advanced nodes. Responsibilities include layout design, verification, and post-silicon support. Requires 5+ years in high-speed/precision analog design.